PIC10LF320 | ||||
---|---|---|---|---|
CONFIG (address:0x2007, mask:0x3FFF) | ||||
FOSC -- Oscillator Selection bits | ||||
FOSC = INTOSC | 0x3FFE | INTOSC oscillator: CLKIN function disabled. | ||
FOSC = EC | 0x3FFF | EC: CLKIN function enabled. | ||
BOREN -- Brown-out Reset Enable | ||||
BOREN = OFF | 0x3FF9 | Brown-out Reset disabled. | ||
BOREN = SBODEN | 0x3FFB | Brown-out Reset controlled by the SBOREN bit in the BORCON register. | ||
BOREN = NSLEEP | 0x3FFD | Brown-out Reset enabled while running and disabled in Sleep. | ||
BOREN = ON | 0x3FFF | Brown-out Reset enabled. | ||
WDTE -- Watchdog Timer Enable | ||||
WDTE = OFF | 0x3FE7 | WDT disabled. | ||
WDTE = SWDTEN | 0x3FEF | WDT controlled by the SWDTEN bit in the WDTCON register. | ||
WDTE = NSLEEP | 0x3FF7 | WDT enabled while running and disabled in Sleep. | ||
WDTE = ON | 0x3FFF | WDT enabled. | ||
PWRTE -- Power-up Timer Enable bit | ||||
PWRTE = ON | 0x3FDF | PWRT enabled. | ||
PWRTE = OFF | 0x3FFF | PWRT disabled. | ||
MCLRE -- MCLR Pin Function Select bit | ||||
MCLRE = OFF | 0x3FBF | MCLR pin function is digital input, MCLR internally tied to VDD. | ||
MCLRE = ON | 0x3FFF | MCLR pin function is MCLR. | ||
CP -- Code Protection bit | ||||
CP = ON | 0x3F7F | Program memory code protection is enabled. | ||
CP = OFF | 0x3FFF | Program memory code protection is disabled. | ||
LVP -- Low-Voltage Programming Enable | ||||
LVP = OFF | 0x3EFF | High-voltage on MCLR/VPP must be used for programming. | ||
LVP = ON | 0x3FFF | Low-voltage programming enabled. | ||
LPBOR -- Brown-out Reset Selection bits | ||||
LPBOR = OFF | 0x3DFF | BOR disabled. | ||
LPBOR = ON | 0x3FFF | BOR enabled. | ||
BORV -- Brown-out Reset Voltage Selection | ||||
BORV = HI | 0x3BFF | Brown-out Reset Voltage (Vbor), high trip point selected. | ||
BORV = LO | 0x3FFF | Brown-out Reset Voltage (Vbor), low trip point selected. | ||
WRT -- Flash Memory Self-Write Protection | ||||
WRT = ALL | 0x27FF | 000h to 0FFh write protected, no addresses may be modified by PMCON control. | ||
WRT = HALF | 0x2FFF | 000h to 07Fh write protected, 080h to 0FFh may be modified by PMCON control. | ||
WRT = BOOT | 0x37FF | 000h to 03Fh write protected, 040h to 0FFh may be modified by PMCON control. | ||
WRT = OFF | 0x3FFF | Write protection off. |
This page generated automatically by the device-help.pl program (2013-05-17 07:55:34 UTC) from the 8bit_device.info file (rev: 1.13) of mpasmx and from the gputils source package (rev: svn 979:980). The mpasmx is included in the MPLAB X.